Field of the Invention
The invention relates to a memory apparatus, and particularly relates to a non-volatile memory apparatus and an operating method thereof.
Description of Related Art
Generally, during an operating process of a solid state disk/drive (SSD) or a memory disk, a mapping table is adopted to record a mapping relationship (or a transforming relationship) between logical addresses and physical addresses. The logical address may include a logical block address (LBA) and/or a logical page address, and the physical address may include a physical block address (PBA) and/or a physical page address. A host generally accesses data stored in the SSD or the memory disk according to variety of modes including page mapping, block mapping, a replacement block or log block, etc. Although the content stored in the mapping table is varied along with the different modes, when the SSD or the memory disk receives an access instruction from the host, the SSD or the memory disk is required to transform a logical address of the access instruction into a physical address of a flash memory in the SSD or the memory disk according to the mapping table, and then the access instruction is executed to a physical memory (a physical block or a physical page) corresponding to the transformed physical address.
During the process of continually executing a plurality of access instructions of the host, the mapping relationship between the logical addresses and the physical addresses can be correspondingly changed, so that the content of the mapping table can be constantly updated. The mapping table is generally stored in a dynamic random access memory (DRAM) to facilitate accelerating an access speed. When a power-off procedure is executed to the SSD or the memory disk, the mapping table is stored in the flash memory of the SSD or the memory disk to avoid losing the content of the mapping table due to the power-off. When the SSD or the memory disk is powered, an initialisation procedure is executed to the SSD. In the initialisation procedure, the SSD or the memory disk may read the mapping table from the flash memory to write back the mapping table to the DRAM.
Generally, a floating gate of a memory cell of the flash memory has a current leakage phenomenon. In case that a writing operation is not performed to the memory cell, along with increase of time, the current leakage phenomenon of the floating gate of the memory cell becomes more and more severe. The current leakage phenomenon of the floating gate of the memory cell may cause an error of bit data. Regarding a physical page of the flash memory, in case that the writing operation is not performed to the physical page for a long time, along with increase of time, an error-bit quantity of the physical page is increased. Generally, the flash memory is configured with an error checking and correcting (ECC) mechanism. When the error-bit quantity in each unit bit quantity (for example, 1K Bytes, or a bit quantity of one physical page) of data is smaller than a certain tolerance quantity, the ECC mechanism may correct the error bits, such that the flash memory may provide correct data to the host. When the error-bit quantity in each unit bit quantity is greater than the tolerance quantity, the ECC mechanism cannot correct the error bits. When the error bits have a large quantity and cannot be corrected, it represents that the data is lost.